The invention relates to the general field of power devices with particular reference to RFLDMOS devices fabricated by standard LDMOS processes and its application in Radio-Frequency (RF) ICs.
High frequency power devices are increasingly needed as an indispensable part in modem personal communication service systems. LDMOSFETs are the only suitable devices on silicon substrates for such applications, the desirable characteristics being high frequency performance, high transconductance, and high blocking voltage. Now the focus is on faster chips that also require less powerxe2x80x94a key requirement for extending the battery life of small, hand-held power devices that will be pervasive in the future. Relatively higher parasitic capacitance and high leakage will limit the achievable application frequency and power dissipation of RF LDMOSFET.
When an FET device is required to operate at high power, means must be found for dissipating the generated heat. To accomplish this, the design illustrated in FIG. 1a has been widely adopted in the industry. In this design, connection to the source is made though lower area 11 which occupies the entire bottom of the device, where it can be directly connected to a heat sink Lower area 11 is connected to source 10 through sinker 12. Both 11 and 12 are of P+ silicon because Pxe2x88x92 region 14 needs to be grounded and metallic shorting bar 15 is provided in order to connect 10 to 12. The remainder of the device is of a standard nature. Gate 16 controls the current flow in the body of the device, across channel region 13, into the drain which is made up of an inner, lightly doped section 18 and an outer, heavily doped section 17.
Unfortunately, Cds the source-to-drain capacitance, is large in designs of the type shown in FIG. 1a because of the relatively thin depletion layer that forms at the N+/Pxe2x88x92 interface. One approach that has been used to overcome this problem has been the design illustrated in FIG. 1b. Here, dielectric layer 33 is inserted between the source, drain and channel regions 10, 17/18, and 14, respectively. This ensures that the magnitude of Cds will be determined by the thickness of 33 rather than by any depletion layers.
The SOI (silicon on insulator) structure shown in FlG. 1b produces devices with smaller junction area, simple Isolation structure, and steeper subthreshold-voltage slopes the bulk devices. Performance dearly profits from the consequent reduction in parasitic capacitance and leakage current, which is appropriate for high frequency and low power dissipation applications. However, at the same time, this SOI structure also has many other drawbacks, such as floating-body effect and low thermal dissipation capability. A quasi-SOI power MOSFET fabricated by reverse silicon wafer direct bonding was recently reported (Satoshi Matsumoto, et al., IEEE Transactions on Electron Devices, vol. 45, no.9, September(1998)1940-1946) to suppress the short channel effect and parasitic bipolar action. However, the device is still with the floating-body effect. Also, the fabrication process was very complicated and difficult to make compatible with standard IC process. Thus, the fabrication of such a device implies a high manufacturing cost.
A routine search of the prior art was performed with the following references of interest being found:
xe2x80x9cApplication of partially bonded SOI structure to an intelligent power device having vertical DMOSFETxe2x80x9dxe2x80x94IEEE ISPSD""97 p309-312 and xe2x80x9cModeling of self-heating effect in thin SOI and partial SOI LDMOS power devicesxe2x80x9dxe2x80x94Solid-State Electronics 43 (1999)1267-1280.
Additionally, in U.S. Pat. No. 5,338,965, Malhi shows a xe2x80x9cpartial SOIxe2x80x9d LDMOS with oxide under the channel, drain and source. Pein (U.S. Pat. No. 5,382,818) and Pein (U.S. Pat. No. 5,378,912) both show various LDMOS devices with different oxide layer configurations. In U.S. Pat. No. 5,777,365, Yamaguchi et al. disclose an LDMOS transistor formed overlying a buried oxide layer for good electrical isolation while Malhi, in U.S. Pat. No. 5,338,965, teaches a SOI MOS combined with RESURF LDMOS.
It has been an object of at least one embodiment of the present invention to provide a semiconductor device having low parasitic capacitance while being capable of operating at relatively high power levels.
Another object of at least one embodiment of the present invention has bean to provide a process for the formation of a buried layer of oxide, of any shape, any size, any thickness, and at any depth.
These objects have been achieved by etching deep trenches into a silicon body. For a preselected depth below the surface, the inner walls of the trenches are protected and oxidation of said walls is then effected until pincer occurs, both inside the trenches and in the material between trenches. The result is a continuous layer of oxide whose size and shape are determined by the number and location of the trenches. Application of the process to the manufacture of a partial SOI RFLDMOS device is also described together with performance data for the resulting structure. The buried oxide layer is inserted only under the LDD and the drain regions, on top of which fabrication processes of the RF LDMOSFET proceed as usual. This structure keeps the same benefits of low parasitic capacitance, low leakage, steeper sub-threshold slope, and good isolation properties as SOI device does. At the same time, the device is xe2x80x9cbulk-likexe2x80x9d and can overcome the drawbacks of full SOI devices, such as floating-body effect and poor thermal dissipation properties.